During the evolution of single chip microcomputers, on-board memory configurations have included various mixtures of random access memory (RAM), mask programmed ROM and programmable ROM that is erasable by ultraviolet (UV) light (EPROM). Historically, electrically erasable programmable read only memory (EEPROM) has evolved more slowly than EPROM. Typically, more silicon space is required to implement EEPROM than EPROM. Endurance, or the ability to withstand many programming cycles, is less with EEPROM than with EPROM. Complementary metal-oxide-silicon (CMOS) technology EEPROM is also prone to latchup problems under high voltage programming stress.
In recent years, however, advances have been made in EEPROM technology, and the gap between it and EPROMs has been closing. As production of 64 kbit EEPROMs grows and 256 kbit EEPROMs become economically feasible, EEPROMs are finding their way into a significant number of applications. Most of these applications utilize the advantages EEPROMs offer over EPROMs which include reduced package costs since no UV window is required to perform a bulk erase. EEPROM provides non-volatile, yet alterable, storage for computer systems. Since it is erasable in-circuit, software updates performed in the field may require nothing more than the user connecting a system to a modem. No disassembly and swapping of EPROMs or ROMs is necessary.
Until now, only small amounts of EEPROM have found their way onto single chip microprocessors. On-board EEPROM opens new doors for single chip microcomputers by providing a relatively large amount of non-volatile, yet alterable storage. However, it must be realized that for any EEPROM array, the address and data buses must be configured and latched for a period of time during programming, and thus execution from that part of the memory is inhibited. Thus, as more and more EEPROM is placed onboard with the microcomputer, and as the EEPROM is used more and more by the user, the central processing unit (CPU) must wait more often to execute from part of the EEPROM if another portion of the EEPROM is still undergoing a programming operation. In addition, as the EEPROMs on chips become larger the time required to test them becomes proportionally larger as well.